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Struttura E Progetto Dei Calcolatori Pdf: A Guide to the Italian Textbook on Computer Architecture

Struttura E Progetto Dei Calcolatori Pdf: A Guide to the Italian Textbook on Computer Architecture

Struttura E Progetto Dei Calcolatori Pdf is a textbook on computer architecture written by David A. Patterson and John L. Hennessy, two renowned experts in the field. The book covers the fundamentals of computer design, from instruction sets and processors to memory and I/O systems, with a focus on the RISC-V architecture. The book also discusses the challenges and opportunities of parallelism, performance, and energy efficiency in modern computing systems.


The book is intended for students and professionals who want to learn about the principles and practices of computer architecture, as well as for those who are interested in the RISC-V architecture, an open-source instruction set that is designed for cloud computing, mobile devices, and other embedded systems. The book is written in Italian and published by Zanichelli in 2019.

The book is available online in pdf format from various sources, such as Anna's Archive[^1^], Arquivo da Anna[^2^], Scribd[^3^], and[^4^]. However, these sources may not be authorized by the authors or the publisher, and may not be safe to download. Therefore, readers are advised to exercise caution when downloading files from the internet, and to respect the intellectual property rights of the authors and the publisher.

The book is divided into seven parts, each covering a different aspect of computer architecture. The parts are:

  • Part I: Fundamentals of Computer Design. This part introduces the basic concepts of computer design, such as performance, cost, power, instruction sets, and arithmetic operations.

  • Part II: Instruction-Level Parallelism and Its Exploitation. This part explores the techniques for increasing the instruction-level parallelism of a processor, such as pipelining, branch prediction, out-of-order execution, and speculation.

  • Part III: Limits on Instruction-Level Parallelism. This part analyzes the factors that limit the instruction-level parallelism of a processor, such as dependences, exceptions, memory latency, and cache coherence.

  • Part IV: Multiprocessors and Thread-Level Parallelism. This part discusses the design and implementation of multiprocessor systems, such as shared-memory and message-passing architectures, synchronization, memory consistency models, and interconnection networks.

  • Part V: Memory Hierarchy Design. This part covers the principles and techniques for designing memory hierarchies, such as caches, virtual memory, cache coherence protocols, and memory protection.

  • Part VI: Storage Systems. This part describes the characteristics and organization of storage systems, such as disks, RAID arrays, solid-state drives, and I/O buses.

  • Part VII: Interfacing Processors and Peripherals. This part explains how processors communicate with peripherals, such as keyboards, mice, displays, printers, scanners, cameras, and network interfaces.

The book also includes appendices that provide additional information on topics such as RISC-V assembly language, floating-point arithmetic, hardware description languages, and parallel programming models. e0e6b7cb5c


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